1. Field of the Invention
The invention relates in general to a multiple T-shaped gate MOSFET device, and more particularly to a MOSFET device, which can increase the ICs' density and speed without physically scaling down the device's channel length and width.
2. Description of the Related Art
In the process of fabricating a MOSFET device, in order to scale down the device, both the channel width and length dimensions are shortened. As the attempt to increase the ULSI device density and speed continues, the technology in the deep sub-micron regime becomes more and more difficult so that it eventually may reach a theoretical limitation. As a result, it is impossible to limitlessly increase the device's density and speed. In addition, the short channel effect will render the technology even more prohibitive. For example, as the channel width and the length dimensions are shortened, punch through of the carriers and the hot carrier effect occur. When the device is even more scaled down, the short channel effect becomes especially significant.
FIGS. 1A to 1H are schematic, cross-sectional views of conventional MOSFET device formation processes. Referring to FIG. 1A, a device includes a substrate 100, a pad oxide layer 102, a silicon nitride layer 104, and a photoresist layer 106. A mask 108 is used to pattern the device. Referring to FIG. 1B, a trench 107 is formed in the substrate 100 by defining the photoresist layer 106, the silicon nitride layer 104, the pad oxide layer 102 and the substrate 100.
The remainder of the photoresist layer 106a and the silicon nitride layer 104a are removed to expose the remainder of the pad oxide layer 102a, as shown in FIG 1C. Referring to FIG. 1D, a dielectric layer 110 is formed in the trench 107 and over the substrate 100. The dielectric layer 110 is polished to expose the substrate 100 and form a shallow trench isolation (STI) structure 110a as shown in FIG. 1E. Then, a gate oxide layer 112, a metal layer 114, and a photoresist layer 116 are formed on the substrate in turn. Next, a mask 118 is further used to pattern the device.
A gate 114a is formed on the substrate 100 by defining the photoresist layer 116, the metal layer 114, and the gate oxide layer 112 as shown in FIG. 1F. Then, the substrate 100 is implanted with ions to form a shallow doped region 111 in the substrate 100. Referring to FIG. 1G, an oxide layer 120 is deposited on the substrate 100. Then, the oxide layer 120 is etched to form spacers 120a besides the gate 114a by dry etching as shown in FIG. 1H. Then, the substrate 100 is implanted with ions to form a deep doped region 113.
The technology will reach a limit in developing high integrity and operating rate. When the device becomes smaller the short channel effect becomes especially apparent.
The references regarding changing the gate shape to increase the integrity and the operating rate are:
1. F. E. Holmes and C.A.T Salama, Solid State Electron, 17.791 (1974) for V-shape MOS.
2. C.A.T Salama, Solid State Electron, 20.1003 (1977) for U-shape MOS.